This invention relates to a data processing circuit for use in calculating either a total sum or a total product of a series of data.
The data processing circuit is used in carrying out calculation of a predetermined one of a total sum and a total product of a plurality of vector data or vector elements which are designated by a vector instruction.
As will later be described with reference to three of several figures of the accompanying drawing, a data processing circuit of the type described may comprise an operand producing section which is responsive to a series of data, such as vector elements, and which successively produces operands two of which will be called a first and a second operand, respectively. The operand producing section is operable on a plurality of pipeline stages. The pipeline stages are carried out under pipeline control of operation of the data processing circuit to carry out the total sum at a high speed. An arithmetic unit successively carries out a local calculation of a local sum of the first and the second operands to produce a local or intermediate result representative of the local sum. The intermediate result is successively delivered as the first operand through the pipeline stages while the data are delivered as the second operand through the pipeline stages.
In the data processing circuit, the intermediate result related to one vector element and a next following vector element are synchronously delivered to the arithmetic unit as the first and the second operands, respectively. That is to say, supply of the next vector element to the operand producing section is postponed or delayed until the intermediate result is calculated by the arithmetic unit for the above-mentioned one vector element. Such a delay time results in an undesiredly slow calculation speed of the data processing circuit. Thus, the calculation speed of data processing circuit is inevitably reduced on calculating the total sum of the series of data.